SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  253 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  966 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 1050 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 1068 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 1574 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT 0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  545 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT	0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  544 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  551 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1
SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT  545 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_WR_IDLE__SHIFT                                                                  0x1