SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  252 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  964 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 1048 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 1066 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 1572 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT 0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  544 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT	0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  543 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  550 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0
SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT  544 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_WREQ_IDLE__SHIFT                                                                0x0