SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  255 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  970 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 1054 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 1072 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 1578 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT 0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  547 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT	0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  546 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  553 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3
SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT  547 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_RREQ_IDLE__SHIFT                                                                0x3