SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  256 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  972 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 1056 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 1074 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 1580 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  548 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT	0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  547 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  554 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4
SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT  548 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_OUT_IDLE__SHIFT                                                                 0x4