SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  257 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  974 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 1058 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 1076 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 1582 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT 0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  549 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT	0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  548 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  555 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5
SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT  549 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_STATUS1_REG__CE_IN_IDLE__SHIFT                                                                  0x5