SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  181 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  902 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  982 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 1000 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 1506 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT 0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  473 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT	0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  472 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  479 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0
SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT  473 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL__TIMER__SHIFT                                                          0x0