SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2783 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2995 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4 SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2985 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC7_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4