SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 2352 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 2574 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0
SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 2564 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC5_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                          0x0