SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2403 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2619 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4
SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2609 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC5_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                            0x4