SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1943 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 2165 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 2155 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC3_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0