SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 1564 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 1768 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT	0x8
SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 1574 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 1790 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8
SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT 1780 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_PENDING__SHIFT                                                         0x8