SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1563 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1767 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT	0x0
SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1573 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1789 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0
SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1779 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC1_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                      0x0