SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1542 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1318 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1456 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1932 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 2242 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1746 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT	0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1552 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1768 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2
SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT 1758 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC1_CONTEXT_STATUS__IDLE__SHIFT                                                                0x2