SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 1344 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 1486 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 1964 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 2274 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__LIMIT__SHIFT 0x10