SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 1342 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 1484 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 1962 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0
SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 2272 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_RLC1_APE1_CNTL__BASE__SHIFT 0x0