SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1275 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1168 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1288 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1736 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 2052 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1485 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT	0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1291 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1503 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10
SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT 1493 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT                                                       0x10