SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 1246 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 1372 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 1822 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10
SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 2138 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_RLC0_APE1_CNTL__LIMIT__SHIFT 0x10