SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT  246 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT	0x1f
SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT  243 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT                                                     0x1f
SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT  246 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT                                                     0x1f
SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT  246 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_UTCL1_WR_STATUS__SHIFT                                                     0x1f