SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 1556 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 1884 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT 0x3
SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT  239 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT	0x18
SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT  236 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT                                                         0x18
SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT  239 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT                                                         0x18
SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT  239 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_STATUS2_REG__SHIFT                                                         0x18