SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 1566 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 1894 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT 0x8
SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT  240 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT	0x19
SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT  237 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT                                                         0x19
SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT  240 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT                                                         0x19
SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT  240 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE1__SDMA0_ATOMIC_CNTL__SHIFT                                                         0x19