SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 1492 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 1820 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT 0x1
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT  161 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT	0x1
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT  158 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT                                                          0x1
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT  161 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT                                                          0x1
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT  161 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_DATA__SHIFT                                                          0x1