SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 1490 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 1818 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT 0x0
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT  160 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT	0x0
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT  157 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT                                                          0x0
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT  160 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT                                                          0x0
SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT  160 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_UCODE_ADDR__SHIFT                                                          0x0