SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 1494 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 1822 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT 0x2
SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT  181 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT	0x1a
SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT  178 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT                                                          0x1a
SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT  181 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT                                                          0x1a
SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT  181 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PUB_REG_TYPE0__SDMA0_POWER_CNTL__SHIFT                                                          0x1a