SDMA0_PHASE1_QUANTUM__VALUE__SHIFT  318 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 1020 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 1110 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 1130 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 1636 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT  604 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT	0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT  603 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT  612 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE1_QUANTUM__VALUE__SHIFT  606 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PHASE1_QUANTUM__VALUE__SHIFT                                                                    0x8