SDMA0_PHASE1_QUANTUM__UNIT__SHIFT  317 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 1018 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 1108 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 1128 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 1634 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT  603 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT	0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT  602 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT  611 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE1_QUANTUM__UNIT__SHIFT  605 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PHASE1_QUANTUM__UNIT__SHIFT                                                                     0x0