SDMA0_PHASE0_QUANTUM__VALUE__SHIFT  311 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 1014 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 1104 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 1124 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 1630 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT 0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT  597 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT	0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT  596 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT  605 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8
SDMA0_PHASE0_QUANTUM__VALUE__SHIFT  599 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PHASE0_QUANTUM__VALUE__SHIFT                                                                    0x8