SDMA0_PHASE0_QUANTUM__UNIT__SHIFT  310 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 1012 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 1102 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 1122 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 1628 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT 0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT  596 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT	0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT  595 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT  604 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0
SDMA0_PHASE0_QUANTUM__UNIT__SHIFT  598 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_PHASE0_QUANTUM__UNIT__SHIFT                                                                     0x0