SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT  993 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1209 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT	0x0
SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1201 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1225 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0
SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT 1215 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_GFX_STATUS__WPTR_UPDATE_FAIL_COUNT__SHIFT                                                       0x0