SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT  927 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1094 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1198 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1610 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1932 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1143 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT	0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1135 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1157 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4
SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT 1147 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_CNTL__FREQUENCY__SHIFT                                                         0x4