SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1022 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1098 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1202 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1614 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1936 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1242 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT	0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1234 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1258 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0
SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT 1248 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_GFX_RB_WPTR_POLL_ADDR_HI__ADDR__SHIFT                                                           0x0