SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1073 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1722 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 2038 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1287 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT	0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1279 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1303 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4
SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT 1293 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_GFX_MIDCMD_CNTL__SPLIT_STATE__SHIFT                                                             0x4