SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT  392 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT  678 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT	0xc
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT  677 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT  685 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT  679 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF5_SED__SHIFT                                                    0xc