SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT  390 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT  676 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT	0xa
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT  675 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT  683 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa
SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT  677 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_EDC_COUNTER__SDMA_MBANK_DATA_BUF3_SED__SHIFT                                                    0xa