SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 360 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 1062 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 1152 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 1172 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 1678 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 646 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 645 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 654 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1 SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 648 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_EDC_CONFIG__DIS_EDC__SHIFT 0x1