SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 40075 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 1488 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0xa
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 1816 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT 0x7
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT	0xa
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT  141 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa
SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT  144 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE2__RESERVED__SHIFT                                                              0xa