SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 40049 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x18
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 1466 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 1800 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT 0x12
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT  117 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT	0x16
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT  114 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT  117 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16
SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT  117 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_CONTEXT_REG_TYPE1__RESERVED__SHIFT                                                              0x16