SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT   92 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  866 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_0_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  936 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  950 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 1456 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT 0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  400 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT	0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  399 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  406 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2
SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT  400 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_CNTL__SEM_WAIT_INT_ENABLE__SHIFT                                                                0x2