SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  132 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  968 drivers/gpu/drm/amd/include/asic_reg/oss/oss_2_4_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  986 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_1_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 1492 drivers/gpu/drm/amd/include/asic_reg/oss/oss_3_0_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT 0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  432 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_0_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT	0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  431 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_1_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  438 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_2_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c
SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT  432 drivers/gpu/drm/amd/include/asic_reg/sdma0/sdma0_4_2_sh_mask.h #define SDMA0_CHICKEN_BITS__CE_DFIFO_WATERMARK__SHIFT                                                         0x1c