RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 11347 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 6312 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 6075 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0
RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT 5954 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define RMI_UTCL1_CNTL2__UTC_SPARE__SHIFT                                                                     0x0