RLC_MEM_SLP_CNTL__RESERVED__SHIFT 33114 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 22745 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 24058 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 24061 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT                                                                     0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 7197 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x00000002
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 7734 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 8548 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2
RLC_MEM_SLP_CNTL__RESERVED__SHIFT 9100 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED__SHIFT 0x2