RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 33118 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 22749 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 24062 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 24065 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT                                                                    0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 7195 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_6_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x00000018
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 7740 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_7_2_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 8556 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18
RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 9108 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_1_sh_mask.h #define RLC_MEM_SLP_CNTL__RESERVED1__SHIFT 0x18