RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 39801 drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_sh_mask.h #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 27349 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 28658 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_1_sh_mask.h #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 29005 drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_2_1_sh_mask.h #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT                                                             0xc
RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 9500 drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h #define RLC_GPU_IOV_SDMA0_STATUS__RESTORED__SHIFT 0xc