RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 12618 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 12624 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 13240 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 56091 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 11516 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT  966 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0
RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT 59156 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define RIRB_STATUS__RESPONSE_INTERRUPT__SHIFT                                                                0x0