RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 12624 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 12630 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 13246 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 56097 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 11522 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT  972 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4
RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT 59162 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY__SHIFT                                                                0x4