RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 12623 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 12629 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 13245 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 56099 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 11521 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 0xf0
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK  974 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L
RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK 59164 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define RIRB_SIZE__RIRB_SIZE_CAPABILITY_MASK                                                                  0x00F0L