RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 12614 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 12620 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 13236 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 56085 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 11512 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT  960 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1
RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT 59150 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE__SHIFT                                                                  0x1