RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 12613 drivers/gpu/drm/amd/include/asic_reg/dce/dce_10_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 12619 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 13235 drivers/gpu/drm/amd/include/asic_reg/dce/dce_11_2_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 56088 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 11511 drivers/gpu/drm/amd/include/asic_reg/dce/dce_8_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 0x2
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK  963 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_1_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L
RIRB_CONTROL__RIRB_DMA_ENABLE_MASK 59153 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_0_sh_mask.h #define RIRB_CONTROL__RIRB_DMA_ENABLE_MASK                                                                    0x02L