REG                63 arch/m68k/lib/divsi3.S #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
REG                63 arch/m68k/lib/modsi3.S #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
REG                61 arch/m68k/lib/mulsi3.S #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
REG                61 arch/m68k/lib/udivsi3.S #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
REG                61 arch/m68k/lib/umodsi3.S #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
REG                33 arch/mips/ar7/irq.c #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
REG              1379 arch/powerpc/kernel/process.c #define REG		"%016lx"
REG              1383 arch/powerpc/kernel/process.c #define REG		"%08lx"
REG               153 arch/powerpc/mm/ptdump/ptdump.c #define REG		"0x%016lx"
REG               155 arch/powerpc/mm/ptdump/ptdump.c #define REG		"0x%08lx"
REG               194 arch/powerpc/xmon/xmon.c #define REG		"%.16lx"
REG               196 arch/powerpc/xmon/xmon.c #define REG		"%.8lx"
REG                40 drivers/block/swim.c #define REG(x)	unsigned char x, x ## _pad[0x200 - 1];
REG                55 drivers/block/swim3.c #define REG(x)	unsigned char x; char x ## _pad[15];
REG                37 drivers/gpio/gpio-it87.c #define REG		0x2e
REG                50 drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c #define REG(reg)\
REG                46 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c #define REG(reg) \
REG                47 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c #define REG(reg_name) \
REG                62 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c #define REG(reg_name) \
REG                44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c #define REG(reg) \
REG                52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c #define REG(reg_name) \
REG                35 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c #define REG(reg_name) \
REG                40 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c #define REG(reg) \
REG                41 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c #define REG(reg)\
REG                37 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c #define REG(reg_name)\
REG                38 drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c #define REG(reg) \
REG                42 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c #define REG(reg)\
REG                40 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c #define REG(reg) \
REG                33 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c #define REG(reg)\
REG                36 drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c #define REG(reg)\
REG                32 drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c #define REG(reg) \
REG                65 drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c #define REG(reg)\
REG                32 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c #define REG(reg)\
REG                35 drivers/gpu/drm/amd/display/dc/dce/dce_opp.c #define REG(reg)\
REG                37 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c #define REG(reg)\
REG                32 drivers/gpu/drm/amd/display/dc/dce/dce_transform.c #define REG(reg) \
REG               392 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c #define REG(reg) mm ## reg
REG                78 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c #define REG(reg)\
REG               433 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c #define REG(reg) mm ## reg
REG               410 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c #define REG(reg) mm ## reg
REG                42 drivers/gpu/drm/amd/display/dc/dce120/dce120_hw_sequencer.c #define REG(reg)\
REG               424 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c #define REG(reg) mm ## reg
REG                32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c #define REG(reg) reg
REG                41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c #define REG(reg)\
REG                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c #define REG(reg)\
REG                42 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c #define REG(reg)\
REG                34 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c #define REG(reg)\
REG                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c #define REG(reg)\
REG                31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c #define REG(reg)\
REG                60 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c #define REG(reg)\
REG                32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c #define REG(reg) \
REG                45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c #define REG(reg)\
REG                29 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c #define REG(reg)\
REG                32 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c #define REG(reg) \
REG                31 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c #define REG(reg)\
REG                37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c #define REG(reg)\
REG                35 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c #define REG(reg) \
REG                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c #define REG(reg)\
REG                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c #define REG(reg)\
REG                64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c #define REG(reg)\
REG                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c #define REG(reg)\
REG                36 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c #define REG(reg)\
REG                31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define REG(reg)\
REG                41 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c #define REG(reg)\
REG                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c #define REG(reg)\
REG                60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c #define REG(reg)\
REG                42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c #define REG(reg)\
REG                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c #define REG(reg)\
REG                33 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c #define REG(reg)\
REG                30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c #define REG(reg) \
REG                30 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c #define REG(reg)\
REG                37 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c #define REG(reg)\
REG                31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c #define REG(reg)\
REG                31 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define REG(reg)\
REG                42 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c #define REG(reg)\
REG                30 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c #define REG(reg)\
REG                45 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c #define REG(reg_name)\
REG                60 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c #define REG(reg_name)\
REG                51 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c #define REG(reg_name)\
REG                41 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c #define REG(reg_name)\
REG                57 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c #define REG(reg_name)\
REG                51 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c #define REG(reg_name)\
REG                60 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c #define REG(reg_name)\
REG                55 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c #undef REG
REG                56 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c #define REG(reg_name)\
REG                58 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c #define REG(reg_name)\
REG                55 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c #undef REG
REG                56 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c #define REG(reg_name)\
REG                46 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c #define REG(reg)\
REG                44 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c #define REG(reg)\
REG                39 drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c #define REG(reg)\
REG                44 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c #define REG(reg)\
REG               101 drivers/gpu/drm/i2c/tda998x_drv.c #define REG(page, addr) (((page) << 8) | (addr))
REG               426 drivers/gpu/drm/tilcdc/tilcdc_drv.c #define REG(rev, save, reg) { #reg, rev, save, reg }
REG               447 drivers/gpu/drm/tilcdc/tilcdc_drv.c #undef REG
REG                41 drivers/hwmon/smsc47b397.c #define	REG	0x2e	/* The register to read/write */
REG                43 drivers/hwmon/smsc47m1.c #define REG	0x2e	/* The register to read/write */
REG               504 drivers/media/tuners/tda18250.c 	#define REG      0
REG               221 drivers/mmc/host/vub300.c #define REG(c) (0x01FFFF & (c->arg>>9))
REG                 9 drivers/net/ethernet/apple/mace.h #define REG(x)	volatile unsigned char x; char x ## _pad[15]
REG                76 drivers/net/ethernet/mscc/ocelot.h #define REG(reg, offset) [reg & REG_MASK] = offset
REG                82 drivers/pinctrl/bcm/pinctrl-nsp-gpio.c 	REG,
REG               428 drivers/pinctrl/pinctrl-ocelot.c #define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))
REG                25 drivers/regulator/rn5t618-regulator.c #define REG(rid, ereg, emask, vreg, vmask, min, max, step)		\
REG               899 drivers/scsi/ncr53c8xx.h #define REG(r) REGJ (nc_, r)
REG               372 drivers/scsi/sym53c8xx_2/sym_defs.h #define REG(r) REGJ (nc_, r)
REG                57 drivers/watchdog/it8712f_wdt.c #define	REG		0x2e	/* The register to read/write */
REG                39 drivers/watchdog/it87_wdt.c #define REG		0x2e
REG               140 fs/proc/base.c #define REG(NAME, MODE, fops)				\
REG                13 tools/perf/arch/arm/util/unwind-libdw.c #define REG(r) ({						\
REG                13 tools/perf/arch/arm64/util/unwind-libdw.c #define REG(r) ({						\
REG                15 tools/perf/arch/csky/util/unwind-libdw.c #define REG(r) ({						\
REG                22 tools/perf/arch/powerpc/util/unwind-libdw.c #define REG(r) ({						\
REG                15 tools/perf/arch/riscv/util/unwind-libdw.c #define REG(r) ({						\
REG                15 tools/perf/arch/s390/util/unwind-libdw.c #define REG(r) ({						\
REG                14 tools/perf/arch/x86/util/unwind-libdw.c #define REG(r) ({						\