RCU_UC_EVENTS__irq31_sel__SHIFT  490 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
RCU_UC_EVENTS__irq31_sel__SHIFT  656 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_1_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
RCU_UC_EVENTS__irq31_sel__SHIFT  656 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_0_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
RCU_UC_EVENTS__irq31_sel__SHIFT  706 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_1_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
RCU_UC_EVENTS__irq31_sel__SHIFT  706 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_2_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
RCU_UC_EVENTS__irq31_sel__SHIFT  734 drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_1_3_sh_mask.h #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18