R4600_V2_HIT_CACHEOP_WAR   14 arch/mips/include/asm/mach-cavium-octeon/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-generic/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   17 arch/mips/include/asm/mach-ip22/war.h #define R4600_V2_HIT_CACHEOP_WAR	1
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-ip27/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-ip28/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-ip32/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-malta/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-pmcs-msp71xx/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-rc32434/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   17 arch/mips/include/asm/mach-rm/war.h #define R4600_V2_HIT_CACHEOP_WAR	1
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-sibyte/war.h #define R4600_V2_HIT_CACHEOP_WAR	0
R4600_V2_HIT_CACHEOP_WAR   13 arch/mips/include/asm/mach-tx49xx/war.h #define R4600_V2_HIT_CACHEOP_WAR	0